Dynamic Random Access Memory (DRAM) is a commonly used type of memory device. A typical memory cell has a transistor and storage capacitor. The capacitor maintains the charge representing a bit of data for a short period of time. Since any real capacitor is going to be imperfect and will leak charge, the memory cell is periodically refreshed.
The DRAM also includes a sense amplifier for sensing a voltage differential that appears between a first bit line and second bit line during a read operation of the memory cell. The sense amplifier determines a binary value of the data represented by the charge maintained in the memory cell by comparing a voltage level corresponding to the charge of the memory cell that is transferred to the first bit line to that of a precharge voltage (e.g., Vdd/2) present on the second bit line. However, since the voltage level within the storage capacitor of the memory cell decays towards ground, the detection of a “high” binary value by the sense amplifier becomes more difficult as the voltage level within the storage capacitor decays closer to the precharge voltage.
In addressing the decaying problem of the storage capacitor, some DRAM circuits use a reference cell to aid the sense amplifier in detecting the “high” binary values by setting a reference voltage within the reference cell to a level below the conventional precharged voltage of Vdd/2 and comparing the reference voltage instead of the conventional precharge voltage to the voltage level of the memory cell. The utilization of the reference voltage set below the traditional precharge voltage increases the margin for detecting the “high” binary value of the memory cell, at the expense of a corresponding decrease in the margin for detecting a “low” binary value of the memory cell.
An example of a circuit that uses a reference cell is shown in FIG. 1. As shown in FIG. 1, the memory cell includes storage capacitor 12 and pass transistor 14. The pass transistor is controlled by a word line signal WL. The reference cell includes capacitor 16 and pass transistor 18, which is controlled by reference word line signal RWL. A pass transistor 20 is coupled between the storage node of the reference cell and reference voltage Veq. Transistor 20 is controlled by precharge signal PRE.
In the DRAM of FIG. 1, the precharge signal PRE keeps the system stable until a row access begins. Simultaneously, the normal and reference word lines WL and RWL are kept off. As a row access begins, the precharge signal is removed and then one word line signal WL and the reference world line signal RWL on the opposite bit line are asserted.
Unfortunately, the current use of the reference cell to increase the margin for detecting the “high” binary value within the memory cell fails to address a problem where the sense amplifier itself may be defective. For instance, the sense amplifier may not have sufficient sensitivity to correctly identify the binary value or voltage level of the memory cell regardless of the setting of the margins.